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An important trend in modern supercomputing is a frequent usage of different architectures and platforms, including various generations of processors, accelerators, various configurations of compute nodes and supercomputers. As a result, now it is necessary more than ever to analyze algorithm properties using a co-design approach, when the most appropriate chain starting from the the problem up to the target architecture should be found. This chain is usually composed from different stages, including the choice of proper algorithms, parallel programming technologies, compilers and implementation approaches. In the presented reseacrh we use a similar approach to investigate methods of solving various large-scale graph processing problems on modern SMP architectures, including Intel Xeon's, Intel KNL processors and Nvidia GPU's. An efficient co-design chain between a specific problem and a target architecture allows us to build high-performance implementations for the architectures mentioned above, capable of processing extremely large graphs, and, moreover, present a fair comparison between those architectures in the context of solving large-scale graph processing problems, which are extremely relevant nowadays in many applications. The results were obtained in the Lomonosov Moscow State University with the financial support of the Russian Science Foundation (agreement № 17-71-20114).