Simulated Annealing Based Placement Optimization for Reconfigurable Systems-on-Chip

Gavrilov, S.; Zheleznikov, D.; Chochaev, R.

Авторы: Sergey Gavrilov, Daniil Zheleznikov, Rustam Chochaev
Сборник: 2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)
Год издания: 2019
Место издания: IEEE
Первая страница: 1597
Последняя страница: 1600
DOI: 10.1109/eiconrus.2019.8657251
Аннотация: Reconfigurable system-on-chip (RSoC) is an integrated circuit that contains reconfigurable logic blocks and hard IP cores, such as microprocessors, RAM, LVDS, multipliers, etc. For successful RSoC design one needs a high-quality CAD system implementing new multilevel placement and routing approaches that take into account the natural hierarchy of the devices. Placement is one of the most important and complex stages in RSoC design flow that impacts the main characteristics of digital circuits. We developed new two-level algorithm for initial placement optimization based on simulated annealing method. To achieve best results we take into account RSoC's features and constraints while performing initial placement and optimization. Placement is performed on 2 levels of hierarchy and allows ready-made IP cores usage. Both global and detailed placement cost functions are developed. The proposed algorithm is implemented and tested using various benchmark suites. Results show that the algorithm generates high-quality routable placement.
Добавил в систему: Железников Даниил Александрович

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